library verilog;
use verilog.vl_types.all;
entity mod_impulse_gen is
    port(
        clk             : in     vl_logic;
        sync_imp        : in     vl_logic_vector(31 downto 0);
        addr            : in     vl_logic_vector(3 downto 0);
        data            : in     vl_logic_vector(31 downto 0);
        wre             : in     vl_logic;
        imp             : out    vl_logic
    );
end mod_impulse_gen;
